Daniel Kovacs
Author

Daniel Kovacs

Daniel Kovacs is a systems architect and technical writer with over 15 years of experience in high-performance computing, enterprise storage, and data center infrastructure. He has designed and deployed large-scale HPC clusters, parallel file systems, and NVMe storage solutions for research institutions and Fortune 500 companies. Daniel holds a Master's degree in Computer Engineering from Georgia Tech and has contributed to open-source projects including Lustre and Ceph. He is passionate about making complex infrastructure topics accessible to IT professionals at every level.

65 Articles

Articles by Daniel

Feb 11, 2026

SLURM

Simple Linux Utility for Resource Management — the dominant open-source job scheduler for HPC clusters and supercomputers.

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Feb 11, 2026

Erasure Coding

A data protection method that encodes data with redundant fragments across multiple locations, offering fault tolerance with less storage overhead…

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Feb 11, 2026

Parallel File System

A distributed file system that stripes data across multiple servers, enabling thousands of clients to access storage concurrently with linear…

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Feb 11, 2026

IOPS

Input/Output Operations Per Second — a key storage performance metric measuring random read/write operation throughput.

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Feb 11, 2026

Ceph

An open-source distributed storage platform providing unified object, block, and file storage with automatic data distribution and self-healing capabilities.

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Feb 11, 2026

Lustre

An open-source parallel file system that powers the majority of the world's top supercomputers, designed for maximum throughput at scale.

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Feb 11, 2026

InfiniBand

A high-bandwidth, low-latency networking technology with native RDMA support, widely used in HPC clusters and AI training infrastructure.

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Feb 11, 2026

NVMe

Non-Volatile Memory Express — a high-performance storage protocol designed for flash SSDs, communicating directly over PCIe for maximum throughput and…

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Feb 11, 2026

RDMA

Remote Direct Memory Access — a technology enabling direct memory-to-memory data transfer between computers without CPU involvement, critical for low-latency…

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